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Research Article

Implementation of Low-Power1-Bit Hybrid Full adder with Reduced Area

  • Paper ID 9
  • Volume 1, Issue 2
  • Pages 11-13
  • Published Online: March-April 2021
  • 8 Views
Open Access Peer Reviewed

Authors

  • G.Arun Kumar1
  • J. Lokesh2
  • K. Sudhanshan3

123Department of Computer Science and Engineering, Jayamukhi Institute of Technological Sciences, Warangal, India.

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Article Information

DOI
No DOI
Published Online
March-April 2021
Pages
11-13
Article Type
Research Article
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  • ISSN 2583-0368
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