Implementation of Low-Power1-Bit Hybrid Full adder with Reduced Area

G.Arun Kumar; J. Lokesh; K. Sudhanshan

Research Article

Implementation of Low-Power1-Bit Hybrid Full adder with Reduced Area

Paper ID 9
Volume 1, Issue 2
Pages 11-13
Published Online: March-April 2021
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Authors

G.Arun Kumar¹
J. Lokesh²
K. Sudhanshan³

¹²³Department of Computer Science and Engineering, Jayamukhi Institute of Technological Sciences, Warangal, India.

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DOI: No DOI
Published In: Volume 1, Issue 2 (2021)
Published Online: March-April 2021
Pages: 11-13
Article Type: Research Article
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Citations

G.Arun Kumar, J. Lokesh, K. Sudhanshan, Implementation of Low-Power 1-Bit Hybrid Full adder with Reduced Area, International Journal Of Recent Trends In Multidisciplinary Research, April 2021, Vol. 1(02), 11-13.

Implementation of Low-Power1-Bit Hybrid Full adder with Reduced Area

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