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Implementation of Low-Power1-Bit Hybrid Full adder with Reduced Area
Published Online: March-April 2021
Pages: 11-13
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No DOIAbstract
In this investigation a low power 1-bithy bridfull snake (FA) and 4-digit full snake circuits where arranged with the proposed 1-bit full adder.By utilizing CMO Sand Pass transistor reasonings another XNOR reasoning is executed. The voltage degradation issue can be over powered by using the CMOS weak inverters.By using this power consumption can be improved.By utilizing two transistors,carry logic module is designed. The circuit is worked at 1.8v. The circuit is designed using 125nm advancement and cow hide treater EDA gadget is used to perform the reenactments. For the proposed plan of full adder the power consumed is of 763.5nW and the delay is 41.03ps.
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