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Original Article

Graphene Nano Ribbon Field-Effect Transistor Based Floating Point Multiplier Topology for Low Power Application

  • Paper ID 385
  • Volume 6, Issue 3
  • Pages 307-316
  • Published Online: May-June 2026
  • 3 Views
Open Access Peer Reviewed Crossref DOI

Authors

  • Kavitha B1
  • Dr. S. Sasikanth2

1 M.E – VLSI DESIGN, Department of Electronics and Communication Engineering, Vivekanandha College of Engineering for Women, Anna university, Namakkal, Tamil Nadu, India. 2 Associate Professor, Department of Electronics and Communication Engineering, Vivekanandha College of Engineering for Women, Anna University, Namakkal, Tamil Nadu, India.

Article Information

Published Online
May-June 2026
Pages
307-316
Article Type
Original Article
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References

[1]. Karimi TKamran A(2025)Energy-Delay Efficient Segmented Approximate Adder With Smart ChainingIEEE Transactions on
Computers10.1109/TC.2024.350037174:2(597-608)
[2]. Z. Li, Z. Lu, W. Jia, R. Yu, H. Zhang, G. Zhou, Z. Liu, and G. Qu, “Efficient Approximate Floating-Point Multiplier With Runtime
Reconfigurable Frequency and Precision,” IEEE Transactions on Circuits and Systems II: Express Briefs ( 2024 ).
[3]. H. Ghabeli, "Design of Floating-Point Multiplier Architecture with Adaptive Data Timing Channels," 2024 6th Iranian International
Conference on Microelectronics (IICM), Tabriz, Iran, Islamic Republic of, 2024, pp. 1-6, doi: 10.1109/IICM65053.2024.10824412.
[4]. Di Meo G, Saggese G, Strollo AGM, De Caro D, Petra N. Approximate Floating-Point Multiplier based on Static
Segmentation. Electronics. 2022; 11(19) :3005. https://doi.org/10.3390/electronics11193005
[5]. Chen, C.; Qian, W.; Imani, M.; Yin, X.; Zhuo, C. PAM: A Piecewise-Linearly-Approximated Floating-Point Multiplier with
Unbiasedness and Configurability. IEEE Trans. Comput. 2021, 71, 2473–2486.
[6]. S. Rezaei, R. Omidi, and A. Azarpeyvand, “Logarithm-approximate floating-point multiplier,” Microelectronics Journal 127, 2022, p.
105521.
[7]. F. Liu, “Improving neural network efficiency via post-training quantization with adaptive floating-point,” in Proc. IEEE/CVF Int. Conf.
Comput. Vis., 2021, pp. 5281–5290.
[8]. Imani, M.; Peroni, D.; Rosing, T. CFPU: Configurable floating point multiplier for energy-efficient computing. In Proceedings of the
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, USA, 18–22 June 2017; pp. 1–6.
[9]. Maram Anantha Guptha, Surampudi Srinivasa Rao, R Selvaraj, “An Efficient Discrete Wavelet Transform Architecture with Low Power
and Multiplier-Less Structure for Pervasive Biomedical Image Processing Application”, EAI Endorsed Transactions on Pervasive Health
& Technology, Volume 9 Issue 1, 2023.
[10]. Imani, M.; Garcia, R.; Gupta, S.; Rosing, T. RMAC: Runtime Configurable Floating Point Multiplier for Approximate Computing. In
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’ 18), Seattle, WA, USA, 23–25 July 2018;
Association for Computing Machinery: New York, NY, USA, 2018; pp. 1–6.
[11]. Zhang, H.; Ko, S.-B. Variable-Precision Approximate Floating-Point Multiplier for Efficient Deep Learning Computation. IEEE Trans.
Circuits Syst. II Express Briefs 2022, 69, 2503–2507.
[12]. Ibrahim, A.; Gebali, F. Enhancing Field Multiplication in IoT Nodes with Limited Resources: A Low-Complexity Systolic Array
Solution. Appl. Sci. 2024, 14, 4085.
[13]. Jiménez, A.; Sauceda, Á.; Muñoz, A.; Duarte, J.; Mireles, J., Jr. FPGA-Based Hardware Implementation of Homodyne Demodulation
for Optical Fiber Sensors. Photonics 2023, 10, 258.
[14]. Tavakkoli, E.; Shokri, S.; Aminian, M. Comparison and design of energy-efficient approximate multiplier schemes for image processing
by CNTFET. Int. J. Electron. 2023, 111, 813-834.
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