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Research Article
Customization of Power Performance in Inter connected MPSOC for NOC
Mahesh Chaudhary1
Ramesh Nath Jha2
Bhawna Sharma3
12Students, Dept. of EEE, Mahabir Engineering College, Haryana, India. 3Asst.Prof, Dept. of EEE, Mahabir Engineering College, Haryana, India.
Published Online: July-August 2023
Pages: 01-04
Cite this article
No DOIReferences
1. D. Bertozzi et al., “ NoC Synthesis Flow forCustomizedDomainSpecificMultiprocessorSystems-on-
Chip,”IEEETransactionsonParalleland Distributed Systems, vol. 16, no. 2, pp113-129,2005.
2. S.-J. Lee et al., “An 800MHz Star-ConnectedOn-Chip Network for Application to Systems on aChip,”IEEEInt.Solid-
StateCircuitsConf.,Feb.2003,pp.468-469.
3. ]K.Leeetal.,“A51mW1.6GHzOn-ChipNetworkforLow-PowerHeterogeneousSoCPlatform,” IEEE Int. Solid-State Circuits Conf.,
Feb.2004,pp.152-153.
4. “Low-PowerNetwork-on-ChipforHigh-Performance SoC Design”, Kangmin Lee, StudentMember, IEEE, Se-Joong Lee, Member,
IEEE, andHoi-JunYoo,SeniorMember,IEEE,IEEETRANSACTIONSONVERYLARGESCALEINTEGRATION (VLSI) SYSTEMS, VOL.
14, NO.2,FEBRUARY2006
Chip,”IEEETransactionsonParalleland Distributed Systems, vol. 16, no. 2, pp113-129,2005.
2. S.-J. Lee et al., “An 800MHz Star-ConnectedOn-Chip Network for Application to Systems on aChip,”IEEEInt.Solid-
StateCircuitsConf.,Feb.2003,pp.468-469.
3. ]K.Leeetal.,“A51mW1.6GHzOn-ChipNetworkforLow-PowerHeterogeneousSoCPlatform,” IEEE Int. Solid-State Circuits Conf.,
Feb.2004,pp.152-153.
4. “Low-PowerNetwork-on-ChipforHigh-Performance SoC Design”, Kangmin Lee, StudentMember, IEEE, Se-Joong Lee, Member,
IEEE, andHoi-JunYoo,SeniorMember,IEEE,IEEETRANSACTIONSONVERYLARGESCALEINTEGRATION (VLSI) SYSTEMS, VOL.
14, NO.2,FEBRUARY2006
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